A silicon semiconductor device equipped with a guard ring in a peripheral portion of a semiconductor chip is well-known. FIG. 31 shows a cross sectional view of this silicon semiconductor device. This semiconductor device is provided with a semiconductor substrate 103 having an N− type epitaxial layer 102 formed on an N+ type silicon semiconductor substrate 101. In a cell portion of this semiconductor device, a P type body region 106 has been formed on a surface layer of the epitaxial layer 102, and an N+ type source region 105 has been formed within the P type body region 106. Also, both a gate electrode 108 and a source electrode 109 have been formed on the semiconductor substrate 103. Also, in an outer peripheral portion which is located at an outer peripheral portion of the cell portion, a P+ type guard ring diffusion layer 110 has been formed in the surface layer of the semiconductor substrate 103 by thermally diffusing an impurity, while a depth of this P+ type guard ring diffusion layer 110 defined from the surface of the semiconductor substrate 103 is made deeper than a depth of the P type body region 106.
As previously explained, since the P+ type layer of the guard ring is deeply formed as compared with the depth of the P type body layer of the cell portion, electric field concentration can be relaxed.
On the other hand, there is a silicon carbide semiconductor device equipped with a vertical type JFET having a trench. FIG. 20 is a cross sectional view for showing a conventional silicon carbide semiconductor device equipped with a JFET. This conventional silicon carbide semiconductor device is provided with an N+ substrate J1 corresponding to a drain region, an N− drift layer J2, an N+ type source layer J3, a P+ type body layer J5, a P+ type gate layer J6, a passivation layer J7, a gate wiring pattern J8, a silicon oxide film J9, a source electrode J10, and a drain electrode J11.
This conventional silicon carbide semiconductor device is manufactured by the below-mentioned method. After the N− type drift layer J2 and the N+ type source layer J3 have been sequentially formed on the N+ type substrate J1, a trench J4 is formed from a surface of the N+ type source layer J3 up to the N− type drift layer J2. Then, an inclined ion implantation is carried out so as to form the P+ type gate layer J6 in a region which is faced to a side plane of the trench J4 within the N− type drift layer J2. In the inclined ion implantation, an implantation angle is inclined with respect to a surface of the substrate. Subsequently, a vertical ion implantation is carried out so as to form the P+ type body layer J5 in a region which is faced to a bottom plane of the trench J4 within the N− type drift layer J2.
Thereafter, the passivation film J7 is formed on a side wall of the trench J4, and the gate wiring pattern J8 is formed on the bottom plane of the trench J4. Furthermore, the silicon oxide film J9 is formed on the gate wiring pattern J8 in such a manner that the internal portion of the trench J4 is embedded. Then, the source electrode J10 is formed in such a manner that the source electrode J10 is formed to connect to the N+ type source layer J3. Also, the drain electrode J11 is formed in such a manner that the drain electrode J11 is formed to connect to the N+ substrate J1. Such a silicon carbide semiconductor device as shown in FIG. 20 may be manufactured in the above-described manner. This device is, for example, disclosed in J. H. Zhao et. al., “3.6 mΩcm2, 1726V 4H—SiC Normally-off Trenched-and-Implanted Vertical JFETs,” in Power Semiconductor Device and Ics 2003, Proceedings, ISPSD 2003 IEEE 15th International Symposium, IEEE, 14-17 Apr. 2003, p. 50-53.
While the silicon carbide semiconductor device manufactured in the above-explained manner owns such a semiconductor structure which flows current from the drain electrode J11 toward the source electrode J10 along with the longitudinal direction, a cell size thereof can be made very narrow, and the memory cells can be integrated in a very fine mode, as compared with that of the semiconductor structure which flows current along with the lateral direction. Also, since the silicon oxide film J9 has been formed on the gate wiring pattern J8 in this silicon carbide semiconductor device, the thickness of this oxide film J9 becomes thick. As a result, there is a merit that an input capacitance of a gate is low.
However, the above-described conventional silicon carbide semiconductor device owns the below-mentioned problems.
As a first problem, an input resistance of the gate is high. As previously explained, since both the P+ type body layer J5 and the P+ type gate layer J6 have been formed in this silicon carbide semiconductor device, both a film thickness J5a of the P+ type body layer J5 and a film thickness J6a of the P+ type gate layer J6 are determined based upon ranges of ion implantation. Also, in the case that ions are implanted with respect to a substrate of a silicon carbide semiconductor, a range of impurity ions is normally small. As a consequence, the film thickness J5a of the P+ type body layer J5 and the film thickness J6a of the P+ type gate layer J6 are smaller than, or equal to 1 μm, namely are thin. As a consequence, the input resistance of the gate becomes high.
It should be understood that as a method for making both a film thickness of a P+ type body layer and a film thickness of a P+ type gate layer thicker, there is such a method for implanting ions that an accelerated voltage has been set to high energy, for instance, several MeV. However, in this ion implantation method, ion implanting apparatus with high energy is required. Also, when the ions are implanted in the high energy, damages may remain when the ions are implanted, and there is a risk that a junction between a gate and a drain may be destroyed. Therefore, this ion implantation method with the high energy is not preferably acceptable.
As a second problem, a withstanding voltage between the gate and the drain is low. In this silicon carbide semiconductor device, the P+ type gate layer J6 owns a shape which is widened along the lateral direction shown in this drawing, and the P+ type body layer J5 owns a shape which is widened along the lower direction shown in this drawing. In other words, a width of the P+ type gate layer J6 along a parallel direction with respect to the substrate surface is different from a width of the P+ type body layer J5 along a vertical direction with respect to this substrate surface. As a result, in this semiconductor device, a step portion J12 is produced in a portion where the P+ type gate layer J6 is located adjacent to the P+ type body layer J5. As a consequence, in such a case that a voltage is applied to this semiconductor device, although not shown in this drawing, an equipotential line has been bent in this step portion J12 in an equipotential distribution. Since electric field concentration occurs in this step portion J12, the withstanding voltage between the gate and the drain becomes low.
As a third problem, a contact resistance between a gate layer and a gate electrode is high. This reason is given as follows. That is, as represented in FIG. 20, while this silicon carbide semiconductor device owns such a structure that the gate wiring pattern J8 and the P+ type body layer J5 have been connected on the bottom plane of the trench J4, a contact area is small because of only the connection between the gate wiring pattern J8 and the P+ type body layer J5. In such a structure, even when an input resistance of a gate is tried to be lowered in order to increase a switching speed, in the case that a cell size is, for instance, 3 μm, or 4 μm, the input resistance of the gate could not be sufficiently lowered.
As a fourth problem, in such a case that while a motor, or the like is connected to the silicon carbide semiconductor device, this silicon carbide semiconductor device is operated, there is a risk that a gate driving circuit is destroyed. That is, when surge energy such as back electromotive force which is produced from an inductance load is applied to this silicon carbide semiconductor device, the surge energy is extracted from the drain electrode J11 via the P+ type body layer J5 to the gate wiring pattern J8. This destruction risk is caused by the following reason. That is, in the silicon carbide semiconductor device having the structure described in Power Semiconductor Device and Ics 2003, Proceedings, ISPSD 2003 IEEE 15th International Symposium, IEEE, 14-17 Apr. 2003, p. 50-53, the P+ type body layer J5 has been connected to the gate wiring pattern J8 on the bottom plane of the trench J4, and no specific measure with respect to the surge energy has been carried out.